自动串并联转换（精选三篇）
自动串并联转换 篇1
1 串并转换电路设计及仿真
在串并转换电路设计中, 设输入数据为8 b位宽, 由输入端输入到串并转换电路中, 将其转换为连续并行输出且位宽为16 b的数据流, 见图1。其中的模块均为基于VHDL语言设计的电路符号, freqdiv为时钟的分频电路, 对输入时钟clock进行2 分频。lpm_ff0 为8bit位宽的D触发器, lpm_ff1 为16 b位宽的D触发器。图2为串并转换的仿真图, 其中clock为输入时钟信号, 在串并转换电路中, 由于输出数据位宽16 b是输入数据位宽8 b的2 倍, 因此数据的输入时钟频率和输出时钟的频率之比为2∶1, 这就需要分频器模块freqdiv对输入时钟进行2 分频。在输入时钟clock的上升沿对输入数据data进行操作, 第一个lpm_ff0 的输出为qo[15..8], 是输入数据data[7..0]延时一个时钟周期的输出, 第二个lpm_ff0 的输出为qo[7..0], 是输入数据data[7..0]延时两个时钟周期的输出, 这两个D触发器的输出并置后, 就组成了位宽为16bit的输出数据qo[15..0]。模块lpm_ff1为16bit位宽的D触发器, 它的工作时钟是输入时钟clock的1/2, 在时钟的上升沿, 对数据qo[15..0]进行触发输出, 得到串并转换后的输出数据q[15..0], 从仿真图 (见图2) 可看出其实现了串并转换的功能[7,8]。
2 并串转换电路设计及仿真
并串转换电路是在输入时钟的作用下, 将16 b位宽的输入数据转换为连续输出的8bit位宽的串行数据输出。其电路结构见图3, 其中lpm_mux0 为二选一的数据选择器, 工作时钟为clock, 模块lpm_counter为计数器, 工作时钟为输入时钟clock的两倍。
图4 为并串转换电路的仿真图, clock为输入时钟, data为位宽为16 b的输入数据, clk_en为计数器使能端, 当其为高电平时进行并串转换, q为并串转换的输出, 从仿真图可以看出其实现了并串转换的功能。
3 串并/并串转换电路总体设计与仿真
将串并转换电路和并串转换电路两个模块连接起来, 就可以实现串并/并串转换电路。在串并/并串转换电路的整体设计中, 首先是数据的输入, 对于不同的数据格式将进行不同转换。如果输入的数据为串行数据, 将进入串并转换模块, 将串行数据转换成并行数据输出。如果输入的数据为并行数据, 将进入并串转换模块, 将并行数据转换成串行数据输出。图5 为是串并转换电路和并串转换电路总体电路, 其中stp为串并转换电路模块, pts为并串转换电路模块。
图6 为串并/并串转换电路总体仿真图, clock为输入时钟, data为位宽为8 b的输入数据, clk_en为计数器使能端, 当其为高电平时进行并串转换, po为串并转换的输出, q为串并转换和并串转换后的输出, 从仿真图可以看出其实现了串并/并串转换的功能。
4 结语
串并转换和并串转换在很多电路系统中都有广泛的应用, 而基于VHDL硬件描述语言设计, FPGA可编程实现的方法, 具有设计周期短、速度快、可靠性高、方便修改及易于大规模集成的优点。
摘要：在数字通信系统的数据传输中, 多数通信数据为串行方式, 而大多数处理器要求数据以并行方式存储和处理, 所以经常需要将串行传输的数据变换成并行传输, 或者将并行传输的数据变换成串行传输, 这时就需要串并/并串转换器。在此介绍了串并/并串转换器基本原理, 并通过QuartusⅡ仿真平台进行仿真验证, 最后下载到FPGA芯片EP1K30QC208-2实现了串并/并串转换器的设计, 仿真及实验结果表明采用此设计方案是可行的。
关键词：串并转换,并串转换,VHDL,FPGA
参考文献
[1]仲建锋, 胡庆生, 孙远.基于FPGA的多路高速串并转换器设计[J].电子器件, 2008 (2) :657-660.
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双电源自动转换控制器英文文献 篇2
A.Farhadi
Abstract: Undesired generation of radiated or conducted energy in electrical systems is called Electromagnetic Interference(EMI).High speed switching frequency in power electronics converters especially in switching power supplies improves efficiency but leads to EMI.Different kind of conducted interference, EMI regulations and conducted EMI measurement are introduced in this paper.Compliancy with national or international regulation is called Electromagnetic Compatibility(EMC).Power electronic systems producers must regard EMC.Modeling and simulation is the first step of EMC evaluation.EMI simulation results due to a PWM Buck type switching power supply are presented in this paper.To improve EMC, some techniques are introduced and their effectiveness proved by simulation.Index Terms: Conducted, EMC, EMI, LISN, Switching Supply I.INTRODUCTION
FAST semiconductors make it possible to have high speed and high frequency switching in power electronics 1.High speed switching causes weight and volume reduction of equipment，2but some unwanted effects such as radio frequency interference appeared.Compliance with electromagnetic compatibility(EMC)regulations is necessary for producers to present their products to the markets.It is important to take EMC aspects already in design phase
3.Modeling and simulation is the most effective tool to analyze EMC consideration before developing the products.A lot of the previous studies concerned the low frequency analysis of power electronics components
45.Different types of power electronics converters are capable to be considered as source of EMI.They could propagate the EMI in both radiated and conducted forms.Line Impedance Stabilization Network(LISN)is required for measurement and calculation of conducted interference level the EMC evaluation criterion
6.Interference spectrum at the output of LISN is introduced as.National or international regulations are the references for
7878the evaluation of equipment in point of view of EMC II.SOURCE, PATH AND VICTIM OF EMI
.Undesired voltage or current is called interference and their cause is called interference source.In this paper a high-speed switching power supply is the source of interference.Interference propagated by radiation in area around of an interference source or by conduction through common cabling or wiring connections.In this study conducted emission is considered only.Equipment such as computers, receivers, amplifiers, industrial controllers, etc that are exposed to interference corruption are called victims.The common connections of elements, source lines and cabling provide paths for conducted noise or interference.Electromagnetic conducted interference has two components as differential mode and common mode 9.A.Differential mode conducted interference
This mode is related to the noise that is imposed between different lines of a test circuit by a noise source.Related current path is shown in Fig.1
9.The interference source, path impedances, differential mode current and load impedance are also shown in Fig.1.B.Common mode conducted interference
Common mode noise or interference could appear and impose between the lines, cables or connections and common ground.Any leakage current between load and common ground could be modeled by interference voltage source.Fig.2 demonstrates the common mode interference source, common mode currents IIand the related current paths
9cm1
and cm2
.The power electronics converters perform as noise source between lines of the supply network.In this study differential mode of conducted interference is particularly important and discussion will be continued considering this mode only.III.ELECTROMAGNETIC COMPATIBILITY REGULATIONS
Application of electrical equipment especially static power electronic converters in different equipment is increasing more and more.As mentioned before, power electronics converters are considered as an important source of electromagnetic interference and have corrupting effects on the electric networks 2.High level of pollution resulting from various disturbances reduces the quality of power in electric networks.On the other side some residential, commercial and especially medical consumers are so sensitive to power system disturbances including voltage and frequency variations.The best solution to reduce corruption and improve power quality is complying national or international EMC regulations.CISPR, IEC, FCC and VDE are among the most famous organizations from Europe, USA and Germany who are responsible for determining and publishing the most important EMC regulations.IEC and VDE requirement and limitations on conducted emission are shown in Fig.3 and Fig.4
79.For different groups of consumers different classes of regulations could be complied.Class A for common consumers and class B with more hard limitations for special consumers are separated in Fig.3 and Fig.4.Frequency range of limitation is different for IEC and VDE that are 150 kHz up to 30 MHz and 10 kHz up to 30 MHz respectively.Compliance of regulations is evaluated by comparison of measured or calculated conducted interference level in the mentioned frequency range with the stated requirements in regulations.In united European community compliance of regulation is mandatory and products must have certified label to show covering of requirements 8.IV.ELECTROMAGNETIC CONDUCTED INTERFERENCE MEASUREMENT A.Line Impedance Stabilization Network(LISN)
1-Providing a low impedance path to transfer power from source to power electronics converter and load.2-Providing a low impedance path from interference source, here power electronics converter, to measurement port.Variation of LISN impedance versus frequency with the mentioned topology is presented in Fig.7.LISN has stabilized impedance in the range of conducted EMI measurement
7.Variation of level of signal at the output of LISN versus frequency is the spectrum of interference.The electromagnetic compatibility of a system can be evaluated by comparison of its interference spectrum with the standard limitations.The level of signal at the output of LISN in frequency range 10 kHz up to 30 MHz or 150 kHz up to 30 MHz is criterion of compatibility and should be under the standard limitations.In practical situations, the LISN output is connected to a spectrum analyzer and interference measurement is carried out.But for modeling and simulation purposes, the LISN output spectrum is calculated using appropriate software.V.SIMULATION OF EMI DUE TO A PWM BUCK TYPE SWITCHINGPOWER SUPPLY
For a simple fixed frequency PWM controller that is applied to a Buck DC/DC converter, it is possible to assume the error voltage(v)changes slow with respect to the switching frequency，ethe pulse width and hence the duty cycle can be approximated by(1).Vp is the saw tooth waveform amplitude.A.PWM waveform spectral analysis
The normalized pulse train m(t)of Fig.8 represents PWM switch current waveform.The nth pulse of PWM waveform consists of a fixed component D/fs , in which D is the steady state duty cycle, and a variable component dn/f sthat represents the variation of duty cycle due to variation of source, reference and load.As the PWM switch current waveform contains information concerning EMI due to power supply, it is required to do the spectrum analysis of this waveform in the frequency range of EMI studies.It is assumed that error voltage varies around Vwith amplitude of Vas is shown in(2).e
e1
fm represents the frequency of error voltage variation due to the variations of source, reference and load.The interception of the error voltage variation curve and the saw tooth waveform with switching frequency, leads to(3)for the computation of duty cycle coefficients10.Maximum variation of pulse width around its steady state value of D is limited to D1.In each period of Tm=1/fm , there will be r=fs/fm pulses with duty cycles of dn.Equation(4)presents the Fourier series coefficients Cn of the PWM waveform m(t).Which have the frequency spectrum of Fig.9.B-Equivalent noise circuit and EMI spectral analysis
To attain the equivalent circuit of Fig.6 the voltage source Vs is replaced by short circuit and converter is replaced by PWM waveform switch current(I)as it has shown in Fig.10.ex
The transfer function is defined as the ratio of the LISN output voltage to the EMI current source as in(5).The coefficients di, ni(i = 1, 2, … , 4)correspond to the parameters of the equivalent circuit.Rc and Lc are respectively the effective series resistance(ESR)and inductance(ESL)of the filter capacitor Cf that model the non-ideality of this element.The LISN and filter parameters are as follows: CN = 100 nF, r = 5 Ω, l = 50 uH, RN =50 Ω, LN=250 uH, Lf = 0, Cf =0, Rc= 0, Lc= 0, fs =25 kHz
The EMI spectrum is derived by multiplication of the transfer function and the source noise spectrum.Simulation results are shown in Fig.11.VI.PARAMETERS AFFECTION ON EMI A.Duty Cycle
The pulse width in PWM waveform varies around a steady state D=0.5.The output noise spectrum was simulated with values of D=0.25 and 0.75 that are shown in Fig.12 and Fig.13.Even harmonics are increased and odd ones are decreased that is desired in point of view of EMC.On the other hand the noise energy is distributed over a wider range of frequency and the level of EMI decreased 11.B.Amplitude of duty cycle variation
The maximum pulse width variation is determined by D.The EMI spectrum was simulated
1with D=0.05.Simulations are repeated with D=0.01 and 0.25 and the results are shown in Fig.14 1
1and Fig.15.Increasing of D1 leads to frequency modulation of the EMI signal and reduction in level of conducted EMI.Zooming of Fig.15 around 7component of switching frequency in Fig.16 shows the frequency modulation clearly.th
C.Error voltage frequency
The main factor in the variation of duty cycle is the variation of source voltage.The fm=100 Hz ripple in source voltage is the inevitable consequence of the usage of rectifiers.The simulation is repeated in the frequency of fm=5000 Hz.It is shown in Fig.17 that at a higher frequency for fm the noise spectrum expands in frequency domain and causes smaller level of conducted EMI.On the other hand it is desired to inject a high frequency signal to the reference voltage intentionally.D.Simultaneous effect of parameters
Simulation results of simultaneous application of D=0.75, D=0.25 and f=5000 Hz that lead
mto expansion of EMI spectrum over a wider frequencies and considerable reduction in EMI level is shown in Fig.18.VII.CONCLUSION
Appearance of Electromagnetic Interference due to the fast switching semiconductor devices performance in power electronics converters is introduced in this paper.Radiated and conducted interference are two types of Electromagnetic Interference where conducted type is studied in this paper.Compatibility regulations and conducted interference measurement were explained.LISN as an important part of measuring process besides its topology, parameters and impedance were described.EMI spectrum due to a PWM Buck type DC/DC converter was considered and simulated.It is necessary to present mechanisms to reduce the level of Electromagnetic interference.It shown that EMI due to a PWM Buck type switching power supply could be reduced by controlling parameters such as duty cycle, duty cycle variation and reference voltage frequency.VIII.REFRENCES
[1] Mohan, Undeland, and Robbins, “Power Electronics Converters, Applications and Design” 3rd edition, John Wiley & Sons, 2003.[2] P.Moy, “EMC Related Issues for Power Electronics”, IEEE, Automotive Power Electronics, 1989, 28-29 Aug.1989 pp.46 – 53.[3] M.J.Nave, “Prediction of Conducted Interference in Switched Mode Power Supplies”, Session 3B, IEEE International Symp.on EMC, 1986.[4] Henderson, R.D.and Rose, P.J., “Harmonics and their Effects on Power Quality and Transformers”, IEEE Trans.On Ind.App., 1994, pp.528-532.[5] I.Kasikci, “A New Method for Power Factor Correction and Harmonic Elimination in Power System”, Proceedings of IEEE Ninth International Conference on Harmonics and Quality of Power, Volume 3, pp.810 – 815, Oct.2000.[6] M.J.Nave, “Line Impedance Stabilization Networks: Theory and Applications”, RFI/EMI Corner, April 1985, pp.54-56.[7] T.Williams, “EMC for Product Designers” 3edition 2001 Newnes.[8] B.Keisier, “Principles of Electromagnetic Compatibility”, 3edition ARTECH HOUSE 1987.[9] J.C.Fluke, “Controlling Conducted Emission by Design”, Vanhostrand Reinhold 1991.[10] M.Daniel,”DC/DC Switching Regulator Analysis”, McGrawhill 1988
[11] M.J.Nave,” The Effect of Duty Cycle on SMPS Common Mode Emission: theory and experiment”, IEEE National Symposium on Electromagnetic Compatibility, Page(s): 211-216, 23-25 May 1989.rd
多路串并转换在超宽带系统中的应用 篇3
UWB(Ultra Wideband)是一种无载波通信技术,利用纳秒至微微秒级的非正弦波窄脉冲传输数据。有人称它为无线电领域的一次革命性进展,认为它将成为未来短距离无线通信的主流技术。UWB通过在较宽的频谱上传送极低功率的信号,能在10米左右的范围内实现数百Mbit/s至数Gbit/s的数据传输速率。UWB具有抗干扰性能强、传输速率高、带宽极宽、消耗电能小、发送功率小等诸多优势,主要应用于室内通信、高速无线LAN、家庭网络、无绳电话、安全检测、位置测定、雷达等领域。
FPGA开发UWB系统时常常需要实现高速串并转换,传统的做法是直接利用FPGA 的内部逻辑资源设计串并转换器,但这样做往往使得串行时钟的最高频率受FPGA 内部资源利用率、布局布线等因素的影响,难以满足设计要求,并最终影响整个系统的性能。随着工艺技术的不断进步与市场需求的日益增加,超大规模、高速、低功耗的新型FPGA不断推出,给高速电路的设计带来了极大的方便[1]。赛灵思(Xilinx)公司在其产品Virtex-5 LX系列中集成了输出并串转换器(OSERDES)和输入串并转换器(ISERDES),它们是专用模块,能够提供高速的I/O处理能力,不受FPGA内部资源的限制,不占用系统逻辑资源。
文中的验证系统采用1片Xilinx Virtex-5FPGA构成验证平台,让其在DDR模式下,实现8路1:6串并转换和6:1并串转换之间的自回环系统,并且实时统计误帧率。
1 仿真实现OSERDES功能
OSERDES:Output Parallel-to-Serial Logic Resources。在Xilinx Virtex-5 FPGA器件中的OSERDES是一个专门的并行到串行转换器,具有特定时钟和设计,以方便高速的执行逻辑资源同步接口。每个OSERDES模块包括一个专用并串转换器和三态控制[2]。数据和三态串行器可配为SDR或者DDR模式。数据序列化可达到6∶1(10∶1,如果使用“SERDES宽度扩展”),三态序列化可以达到4∶1。
在ISE的环境下,基于Virtex-5设计了2路6∶1并串转换器。6位并行数据被接入OSERDES的D1到D6端口,串行数据传输时钟iobclk被接入OSERDES的CLK端口,并行数据传输时钟clkdiv被接入OSERDES的CLKDIV端口。其中,CLK和CLKDIV应该满足CLK=3×CLKDIV。
使用ModelSim SE6.5仿真工具,基于Virtex-5的2路6:1并串转换器,其仿真结果如图1所示。其中,串行时钟iobclk的频率为40MHz , 经DCM的三分频后,clkdiv频率为13MHz ,按照DDR 方式传送数据。
如图1仿真时序所示:
事件1:在分频时钟clkdiv的上升沿,由FPGA逻辑产生并驱动的并行数据PD(100001)到达OSERDES端口(方框所示);
事件2:在分频时钟clkdiv的上升沿,并行数据PD(100001)被OSERDES端口采样进入OSEDER进行并串转换;
事件3:分频时钟clkdiv有效后,再经过3个iobclk周期的延迟,6位的串行数据sData0 输出:10001。
2 仿真实现ISERDES功能
ISERDES(Iutput Serial-to-Parallel Logic Resources),在Xilinx Virtex-5 FPGA器件中的是一个专门的串行到并行转换器,具有特定时钟和设计,以方便高速的执行逻辑资源同步接口。每个ISERDES模块包括一个专用串并转换器,可编程延迟单元,比特偏移模块和时钟使能模块[2]。数据转换可配为SDR或者DDR模式。数据序列化可达到1∶6(1∶10,如果使用“SERDES宽度扩展”)。
在ISE的环境下,基于Virtex-5设计了1路1∶6并串转换器。6位串行数据被接入ISERDES的D端口,串行数据传输时钟iobclk被接入ISERDES的CLK端口,并行数据传输时钟clkdiv被接入ISERDES的CLKDIV端口。其中,CLK和CLKDIV也应该满足CLK=3×CLKDIV。
使用ModelSim SE6.5仿真工具,基于Virtex-5的1路1∶6串并转换器,其仿真结果如图2所示。 其中,串行时钟iobclk的频率为40MHz, 经DCM的三分频后,clkdiv频率为13MHz,按照DDR方式采样数据。
如图2仿真时序所示:
事件1:在串行时钟iobclk的上升沿和下降沿均采样串行数据sData,此时刻采样到的串行数据为:000001;
事件2:在并行时钟clkdiv有效后,再经过三个iobclk周期的延迟,6位的并行数据pd输出;
事件3:并行数据pd输出的数据为000010;在经过一个右移位操作,得到我们想要的并行数据pds,此时采样到的pds为:000001。
3 在硬件验证平台上实现OSERDES-ISERDES并统计误帧率
在UWB硬件验证平台上,通过专用的LVDS线缆把OSERDES-ISERDES连接起来,形成8路1:6串并转换和6:1并串转换之间的回环,误帧率统计如下:
在40MHz时钟下,UWB平台上统计低速OSERDES-ISERDES的误帧率,如表1所示。
在132MHz时钟下,UWB平台上统计高速OSERDES-ISERDES的误帧率,如表2所示。
4 结束语
从表1-2的数据统计结果可知,输入OSERDES的源数据和ISERDES输出的目标数据,两者相同。说明OSERDES-ISERDES回环工作正常,设计实现了串并转换功能并且可以无差错的高速传输。
参考文献
[1]仲建锋,胡庆生,孙远.基于FPGA的多路高速串并转换器设计[J].电子器件,2008,31(2).